UNITA' DI CATANIA

UNIVERSITA’ DEGLI STUDI DI CATANIA

Dipartimento di Ingegneria Elettrica, Elettronica e Informatica

STMicroelectronics - Catania

 

Research topics


1.         MODELING AND DESIGN OF ANALOG CIRCUITS

G. Palumbo, S. Pennisi 

Collaborations: University of Sevilla, Università Sapienza - Roma, STMicroelectronics

 

2.         MODELING AND DESIGN OF DIGITAL CIRCUITS AND SYSTEMS

G. Giustolisi, G. Palumbo

Collaborations: Università di Siena, STMicroelectronics

 

3.          INTEGRATED CIRCUITS FOR RF AND MM-WAVE APPLICATIONS

E. Ragonese, G. Palmisano

Collaborations: STMicroelectronics, Agilent Technologies

 

4.          RAD-HARD NEW PRODUCT & TECHNOLOGY DEVELOPMENT, IMS R&D, STMICROELECTRONICS

A. Imbruglia

Collaborations: CERN, Space, ESA, CNES

 

MODELING AND DESIGN OF ANALOG CIRCUITS
 
G. Palumbo, S. Pennisi

The gain-bandwidth conflict is one the most important limitations of high gain feedback amplifiers. In [1]-[2] we discussed in a unified manner many of the possible approaches aimed to design amplifiers with a constant closed-loop bandwidth. Advantages and drawbacks are evidenced and new potential solutions are also formulated.

With the progressive reduction of MOS transistors minimum dimension and their associated supply voltages, the body terminal –considered in the past as an exclusive source of unwanted second order effects– has been advantageously exploited by digital designers and is also becoming an attractive opportunity for the implementation of high-performance analog integrated circuits. We discussed in [3] some techniques that can be applied to many conventional analog building blocks in order to improve their performance (such as gain and linearity) and/or decreasing their supply demand. Experimental prototypes have been implemented and tested, showing that the proposed techniques are promising candidates for enhanced analog IC design in nanoscale technologies.

With the introduction of high-current 8-inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In [4], we presented the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes.

An accurate behavioral model for simulating Single-Photon Avalanche Diodes (SPADs) has been presented [5]. The device operation is described using the Verilog-A description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of a SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach.

Three representative class AB Current Mirror OTAs have been analytically compared in term of the tradeoffs among speed, current consumption and area [6]-[7]. The approach presented allows to derive useful design guidelines. The analysis was validated by means of simulations in a 90 nm CMOS technology. In [8] an improved and compact low-power high-speed buffer amplifier topology for large-size liquid crystal display drivers was proposed. Simulation results demonstrate that the suggested buffer can drive a 1000-pF column line capacitive load with a 5.8-V/ms slew-rate and a 0.75-ms settling time, while drawing only 3-mA quiescent current from a 3-V power supply.

The design of a low-voltage CMOS tunable transconductor with gain boosting enhancement is presented in [9]. The novelty of the proposed OTA is based on the use of bulk-driven techniques to increase its gain. Moreover, the tunability of the transconductor is achieved by varying the current that biases the gain boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology from a 1.2-V power supply. Simulations show that the demanding features of the Ultra Low Power Bluetooth Standard are all met.

A design procedure for high-order continuous time low-pass filters based on the cascade of biquadratic cells is presented in [10]. Compared to the standard design approach of a 10-pole Gm-C filter and using a 65-nm CMOS process, the proposed one achieves a noise reduction from 8.2 mVrms to 4.9 mVrms and a dynamic range improvement of 4.1dB.

 
Pubblications 2011

1)         S. Pennisi, G. Scotti, A. Trifiletti, “Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers,” IEEE Transactions on Circuits and Systems-part I, Vol. 58, No. 9, pp. 2108–2113, Sep. 2011.

2)         S. Pennisi, G. Scotti, A. Trifiletti, “Reply to Comment on Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers,” IEEE Transactions on Circuits and Systems-part I, Vol. 58, No. 9, p. 2117, Sep. 2011.

3)         P. Monsurrò, S. Pennisi, G. Scotti and A. Trifiletti, “Exploiting the Body of MOS Devices for High Performance Analog Design,” IEEE CAS Magazine, Vol. 11, No. 4, pp. 8–23, Nov. 2011.

4)         S. Pennisi, F. Pulvirenti, A. La Scala,  “Low-Power Cool Bypass Switch for Hot Spot Prevention in Photovoltaic Panels”, ETRI Journal, Vol. 33, No. 6, pp. 880–886, Dec. 2011.

5)         G. Giustolisi, R. Mita, G. Palumbo, "Verilog-a Modeling of SPAD Statistical Phenomena", ISCAS’11, Rio de Janeiro, pp. 773-776, May 2011.

6)         G. Palumbo, M. Pennisi, R. G. Carvajal, "Figures of Merit for Class AB Input Stages", ECCTD’11, Linköping, pp. 778-781, September 2011.

7)         G. Palumbo, M. Pennisi, R. G. Carvajal, "Analysis and Comparison of Class AB Current Mirror OTAs", Analog Integrated Circuits and Signal Processing, Vol. 67, No. 2, pp. 231-239, May 2011.

8)         D. Marano, G. Palumbo, S. Pennisi, “Self-biased Dual Path Push-Pull Output Buffer Amplifier Topology for LCD Driver Applications”, ISCAS '11, pp. 29-32, Rio de Janeiro, Brazil, May 2011.

9)         T. Sánchez-Rodríguez, R.G. Carvajal, S. Pennisi, R. Galan, “0.13-µm CMOS Tunable Transconductor Based on the Body-Driven Gain Boosting Technique with Application in Gm-C Filters,” ECCTD 2011, Linkoping, Sweden, pp. 145-148, Aug. 2011.

10)     P. Monsurrò, S. Pennisi, G. Scotti, A. Trifiletti,  “Design Strategy for Biquad-Based Continuous-Time Low-Pass Filters”, ECCTD 2011, Linkoping, Sweden, pp. 394-397, Aug. 2011.

 

MODELING AND DESIGN OF DIGITAL CIRCUITS AND SYSTEMS

G. Giustolisi, G. Palumbo

A novel gate-level strategy for designing Carry-Select adders was proposed [1]. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover the strategy is simple and systematic, and is helpful for designing Carry-Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design.

An extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects) [2]-[4]. Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, starts from an optimum design strategy. The comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology carried out permits to derive several considerations on each FF class and to identify the best topologies for a targeted application. Moreover, a novel optimized design strategy for transmission-gate-based master–slave (TGMS) FF has been proposed[5]. The approach allow to achieve significant improvements on delay and, remarkably, on energy and area occupation.

An ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed [6]. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear ID versus VDS relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. The model is shown to allow an accurate and quick estimation of DC transfer curves or SRAM noise margins [7].

 

Pubblications 2011

1)         M. Alioto, G. Palumbo, M. Poli, "Optimized Design of Parallel Carry-Select Adders", Integration – The VLSI Journal, Vol. 44, No. 1, pp. 62-74, January 2011.

2)         M. Alioto, E. Consoli,  G. Palumbo, "DET FF Topologies: a Detailed Investigation in the Energy-Delay-Area Domain", ISCAS’11, Rio de Janeiro, pp. 563-566, May 2011.

3)         M. Alioto, E. Consoli, G. Palumbo, "Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies", IEEE Trans. on VLSI, Vol. 19, No. 5, pp. 725-736, May 2011.

4)         M. Alioto, E. Consoli, G. Palumbo, "Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit", IEEE Trans. on VLSI, Vol. 19, No. 5, pp. 737-750, May 2011.

5)         E. Consoli,  G. Palumbo, M. Pennisi,  "TG Master-Slave FFs: High-Speed Optimization", ISCAS’11, Rio de Janeiro, pp. 554-557, May 2011.

6)         E. Consoli, G. Giustolisi, G. Palumbo, "An Ultra-Compact MOS Model in Nanometer Technologies", ECCTD’11, Linköping, pp. 541-544, September 2011.

7)         E. Consoli, G. Giustolisi, G. Palumbo, "Inverter Transfer Curves and SRAM Noise Margin Evaluation Based on an Ultra-Compact MOS Model", ECCTD’11, Linköping, pp. 533-536, September 2011.

 

INTEGRATED CIRCUITS FOR RF AND MM-WAVE APPLICATIONS

E. Ragonese, G. Palmisano

This research activity is focused on Si-based ICs for RF/mm-wave applications.

The research in the mm-wave area has been addressed to the evaluation of novel circuit solutions and the design of 24/77-GHz blocks for SR/LR automotive radar.

A SiGe BiCMOS 24-GHz I/Q RX front-end for an UWB SRR sensor is presented in [1]. It achieves a 30-dB gain, a 6-dB noise figure, a phase noise of -104dBc/Hz at 1‑MHz offset from the 24-GHz carrier and a 4.7‑GHz tuning range.

In [2], a transformer-coupled cascode amplifier topology is compared with the most used PA solutions, using a 65‑nm CMOS node at 60-GHz operating frequency and 1.2-V supply voltage. The proposed topology improves small/large‑signal performance, thus proving effectiveness with sub-µm CMOS and mm-wave operation.

A 77-GHz two-stage pseudo-differential PA implemented in a 160/175-GHz fT/fmax SiGe BiCMOS technology is presented in [3]. The amplifier performance is considerably improved thanks to input/output LC resonant networks, which cancel out the ground-plane parasitic effect. The PA achieves a power gain of 18.5dB, a maximum POUT of 11.6dBm, with 4.2% PAE, and an OP1dB of 9.3dBm.

Papers [4] and [5] describe two 77-GHz PAs fabricated in a 230/280-GHz fT/fmax SiGe BiCMOS technology. The circuit in [4] consists of a two‑stage pseudo-differential cascode with fully integrated input/output matching networks. The PA has a FOM of 2500 achieving a 22.5-dB power gain and a PAE of 7.5%. The pseudo-differential PA in [5] adopts a transformer‑coupling current‑reuse approach to improve both gain and efficiency. An interstacked transformer is adopted to reduce output losses due to the differential-to-single-ended conversion. The PA exhibits a PSAT, a peak PAE, and a gain of 14.5dBm, 9%, and 25dB, respectively, thus achieving a first-rate FOM of 4755. A focus on interstacked transformers for mm-wave applications is also discussed in [6].

Efforts have been devoted to the topic of sub-GHz ultra-low-power applications.

In [7], a 90-nm CMOS ultra low-power 0.3-1GHz auto-calibrated I/Q generator is presented. The circuit is based on master-slave dividers, which are closed in a delay-locked feedback loop. The phase error is lower than 3.5 degrees with respect to process tolerances, temperature and power supply variations. It becomes lower than 1 degree using a digital tuning of the loop reference voltage. The current consumption is 0.5mA from a 1.2-V supply.

In [8], a 90-nm CMOS low-power wideband LC VCO is proposed. Wide tuning range, low phase noise, and low power consumption are achieved thanks to the adopted LC tank, which is based on shunt-connected switched‑coupled inductors and A-mode thin and thick MOS varactors. The VCO exhibits a phase noise at 1-MHz offset frequency lower than -114dBc/Hz over the entire tuning range (i.e., 1.13-1.9GHz). It has the outstanding PFTN FOM of 10. The VCO core die area is 0.5mm2.

The topic of RF energy harvesting for WSNs has been also addressed.

A 90-nm CMOS 915-MHz energy harvester for RF-powered sensor networks is presented in [9]. It takes advantage of an improved multi-stage rectifier topology and a CAD‑oriented design methodology to maximize the power conversion efficiency. The harvester is able to deliver a 1.2‑V dc output to 1-MΩ load with input power of -18.8 dBm.

In [10], a batteryless CMOS RF transceiver for WSN nodes is proposed. It includes a receiver for symmetrical RX/TX throughput and exploits narrowband active transmission to improve the uplink reading range without burdening the reader complexity. A PLL-based architecture is adopted both to recover incoming data and synthesize the TX carrier from the input RF signal. This enables crystal-less operation, thus minimizing the system complexity and cost.


Finally a 90-nm CMOS LNA for 3-10-GHz UWB applications is presented in [11]. The circuit adopts a single-ended dual-stage solution. It exhibits a 12.5-dB power gain in a 7.6-GHz 3-dB bandwidth, a minimum noise figure of 3dB, a reverse isolation better than 45dB up to 10.6GHz, and a record small group-delay variation of ± 12 ps. The LNA draws 6 mA from a 1.2-V power supply.
 

Pubblications 2011

1)         E. Ragonese, A. Scuderi, V. Giammello, and G. Palmisano, “A SiGe BiCMOS 24‑GHz receiver front-end for automotive short-range radar,” Springer Analog Integrated Circuits and Signal Processing, vol.67, pp.121-130, May 2011.

2)         V. Giammello, E. Ragonese, and G. Palmisano, “Transformer-coupled cascode stage for mm-wave power amplifiers in sub-μm CMOS technology,” Springer Analog Integrated Circuits and Signal Processing, vol.66, pp.449-453, March 2011.

3)         V. Giammello, E. Ragonese, and G. Palmisano, “A 77-GHz PA with ground‑plane parasitic cancellation in a SiGe HBT BiCMOS technology,” Wiley Microwave and Optical Technology Letters, vol.53, pp.1413-1416, June 2011.

4)         V. Giammello, E. Ragonese, and G. Palmisano, “A 15-dBm SiGe BiCMOS PA for 77-GHz automotive radar,” IEEE Trans. Microwave Theory and Tech., vol.59, n.11, pp.2910-2918, Nov. 2011.

5)         C.M. Ippolito, A. Italia, and G. Palmisano, “A CMOS auto-calibrated I/Q generator for sub-GHz ultra low-power transceivers,” IEEE Radio Frequency Integrated Circuits Symp. Dig. (RFIC 2011), June 2011, pp. 1-4.

6)         G. Papotto, F. Carrara, and G. Palmisano, “A 90-nm CMOS threshold‑compensated RF energy harvester,” IEEE J. Solid-State Circuits, vol.46, n.9, pp.1985‑1997, Sep. 2011.

7)         G. Sapone, and G. Palmisano, “A 3-10-GHz low-power CMOS low-noise amplifier for ultra-wideband communication,” IEEE Trans. Microwave Theory Tech., vol.59, n.3, pp.678-686, March 2011.

 

RAD-HARD NEW PRODUCT & TECHNOLOGY DEVELOPMENT, IMS R&D, STMICROELECTRONICS

A. Imbruglia

Among the proprietary technologies of STMicroelectronics, IMS R & D develops appropriate technology, with improved performance for harsh environments (Space, CERN).

The research and development works on rad-hard technology platforms, while the design centers of division of Catania, Agrate and Grenoble use these platforms to design and qualify products.

Our site ST Rennes, in France, is fully qualified to handle the back-end operations on the legislation for the space.

Because of the complexity of the aerospace, there is the need of some support from both European and national agencies. Some projects are developed in cooperation between ST and the Agencies, using a partial funding from them.

During 2011, the development of rad-hard technologies, IMS R&D in collaboration with departments, has continued with the following activities/results:

1. Development of PowerMOSFET, PWM controller, Integrated Current Limiter, Low Side PowerMOS Drivers with ESA and CNES contracts by means of financing.

2. Feasibility study and radiation testing of technologies and BCD and BCDSOI.

3. Cooperation with ASI to define developments.

New products for space applications: RHF484 DSCC qualified. RHF330, RHF350 QmlV qualified. SMD-1N58x06 Diodes, 1N5811, 1N5819, 1N5822, 1N6640 and 1N6642 now fully qualified ESA.

Congress & Meetings: As part of the European Component Initiative I and II there were several meetings on the progress with ESA and CNES. Other meetings: ST ASI Meeting in Rome, April 6, 2011. Harmonization meeting in ESTEC, September 7, 2011.

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