Dipartimento di Elettronica e telecomunicazioni

Research topics

1.         System level design of embedded systems

L. Lavagno

Collaborations: Cadence Design Systems, Thomson Security, STMicroelectronics, Ecole Nationale Superieure, University of Genova 

2.         Asynchronous circuit design

L. Lavagno

Collaborations: STMicroelectronics


3.         Architectural design of Wireless Sensor Network nodes

L. Lavagno

Collaborations: The Mathworks, STMicroelectronics, INTECS, Technical University of Crete, University of Napoli, Universitat Politecnica de Madrid, Istituto Superiore Mario Boella



G. Ghione

Collaborations: Università di Roma “Tor Vergata”, SELEX-SI, Università di Roma Tre, IFN-CNR Roma.



G. Ghione, M. Goano

 Collaborations: Department of Electrical and Computer Engineering, Boston University, USA; Dipartimento di Ingegneria dell'Informazione, Università di Padova; University of Cambridge, Department of Materials Science and Metallurgy.


System level design of embedded systems

L. Lavagno

The massive investments required to set up semiconductor fabrication facilities will force electronics companies to focus increasingly on their core competencies. Therefore there is a need for the use of disciplined, re-use based, design methods that can reduce substantially design and verification time and for a design environment that can support the entire design chain. To support it efficiently, the design methodology and associated tools and flows must start capturing the design specifications at the highest level of abstraction and proceed towards an efficient implementation.

In this research we are working on a design methodology and a tool to synthesize either a Simulink model or an untimed SystemC specification of a reusable hardware block, down to the Register Transfer level. As a part of this effort, we are also investigating profiling-based methods for discovering potential parallelism in a legacy sequential application, for multi-core or heterogeneous hardware/software implementation.

Our specific contributions in this area are on the Simulink/SystemC front-end side, experimenting with methods to generate effectively synthesizable SystemC models from Simulink models.

We are also looking at data profiling techniques to analyze data dependencies between sections of code, thus enabling manual or computer-assisted decomposition into concurrent, pipelined threads for hardware (and multi-core software) implementation.  This research is supported by the FP7 HEAP and PHARAON projects.


Publications in 2011

1)         S. A. Butt,L. Lavagno (2011). Model-based rapid prototyping of multirate digital signal processing algorithms. 1- 4, In:NORCHIP. 2011-nov.

2)         P. Sayyah,S. A. Butt,L. Lavagno (2011). Simulink-based hardware/software trade-off analysis technique. 1- 7, In:Applied Electrical Engineering and Computing Technologies (AEECT). 2011-dec

3)         S. Butt,P. Sayyah,L. Lavagno (2011). Model-based hardware/software synthesis for wireless sensor network applications. 1- 6, In:Electronics, Communications and Photonics Conference (SIECPC) 2011-apr

4)         Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe: Realistic performance-constrained pipelining in high-level synthesis. DATE 2011

Asynchronous circuit design

L. Lavagno

The goal of this work is to enable a synchronous designer to pick up as many advantages of asynchronous circuits as possible, without leaving familiar territory in terms of tools, languages and flows.

After exploring the translation of synchronous circuits into asynchronous ones in the ``desynchronization'' project, we are now considering high-level synthesis techniques starting from SystemC and aimed at an asynchronous handshaking implementation. The approach that we are using is based on Petri nets and includes aspects such as timing optimization, exploitation of commutative rewritings of an arithmetic expression, and trade-offs between exact and heuristic algorithms. The activity is partially funded by the ENIAC project Modern.

More recently, we started working on using resilient design techniques, based on so-called Razor Flops, in which each flip-flop is split into two, one clocked faster than the worst-case delay, and one clocked slower. These techniques, show great promise to reduce the power consumption and improve the performance of digital design, by reducing the margins that must be taken at design time to tolerate process and operating condition variability. However, in the synchronous case they are subject to unsolvable meta-stability problems. By using an asynchronous or Globally Asynchronous Locally Synchronous clocking scheme, the local clocks can be reliably stopped while the flip-flops resolve metastability, and thus result in a Safe Razor architecture.

Publications in 2011

1)         Andrikos N., Lavagno L. (2011). Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis. 13- 21, In:ASYNC 2011, 17th IEEE International Symposium on Asynchronous Circuits and Systems. April 27-29, 2011

Architectural design of Wireless Sensor Network nodes

L. Lavagno

Our research activity on Wireless Sensor Networks (WSNs) focuses on the problem of efficient HW and SW architectural design of WSN platforms.

We are currently investigating the limitations of current WSN design methodologies, with particular care to ease of modeling, simulation and code generation for the target platform. The first research results involved the use of Simulink and Stateflow for modeling and simulation, and of Embedded Coder to generate quickly code for multiple platforms (TinyOS, Mantis, ZigBee).

This activity is carried out in close cooperation with the Sensor Network group of STMicroelectronics in Agrate, and with several other groups in Italy and abroad. In particular, it is financed by the FP7 IST project Complex, whose objective is to develop a model-driven architectural exploration flow for embedded systems including WSNs.

Publications in 2011

1)         Khan S. U., Lavagno L., Pastrone C., Spirito M. (2011). An effective key management scheme for mobile heterogeneous sensor networks. 98- 103, ISBN:9780956426383 . In:International Conference on Information Society. 27-29 June 2011

2)         S. U. Khan; C. Pastrone; L. Lavagno; M. A. Spirito (2011). An Energy and Memory-Efficient Key Management Scheme for Mobile Heterogeneous Sensor Networks. 1- 8, In:Risk and Security of Internet and Systems (CRiSIS). 26-28 Sept. 2011


G. Ghione

An intensive characterization campaign on GaN HEMTs devices fabricated by Selex-SI on SiC substrates and different lithography processes has been accomplished. Power characterization with Pin-Pout and Load/Source-Pull measurements at the fundamental and second harmonic have been carried out in order to assess the degree of maturity of GaN devices. The characterization activity has been carried out within the PRIN research project “Transistori ad effetto di campo ad alto breakdown per applicazioni ad elevata potenza ed efficienza”. The labs capabilities for the non linear characterization of high power GaN devices have also been intensively used within the European project Korrigan (Key Organization for Research on Integrated circuits in GaN Technology), sponsored by the European Defence Ministries aimed at promoting activities on GaN technologies in Europe.  The microwave group has tested and evaluated various GaN devices fabricated within the project, providing the experimental data for device model extraction and validation.

From the modeling standpoint, significant achivements concern the power device electrothermal modeling. A novel approach to include accurate dynamic thermal effects to a temperature-dependent device model has been developed. The electrical model is based on a temperature-dependent large-signal equivalent circuit while an accurate, albeit computationally efficient, compact dynamic thermal model has been extracted through a {\em Wiener behavioral approach} from full-scale 3D-FEM simulations. The thermal model extraction strategy allows to model devices with a given layout and epitaxial structure both in backside and flip chip configuration.

The model is implemented into the ADS RF circuit simulation environment, thus enabling to explore the detailed influence of the thermal dynamics on the device performances (thermal memory effects) under complex modulated excitation and in different power stages (class A, AB or B). By exploiting such a model, the RF behavior of GaN power devices with different mounting solutions can also be investigated.

Recently, the group has started a collaboration with Università Roma Tre (prof. G. Conte) and Università Roma Tor Vergata (prof. E. Limiti) in the field of microwave devices developed on hydrogenated diamond, including Power characterization with Pin-Pout and Load/Source-Pull measurements and the development of physics-based semi-analytical models.



G. Ghione, M. Goano

The relative technological immaturity of novel narrow- and wide-band gap semiconductors requires the theoretical determination of electrical and optical parameters necessary for device design.  We have developed a set of software tools for the computation of the electronic structure of zincblende and wurtzite semiconductor compounds and alloys. These tools have been applied to various SiC polytypes, to III-N binary compounds and ternary alloys, and to II-VI material systems such as HgCdTe, ZnO and BeO. The information thus obtained has been the main prerequisite for the quantitative determination of low- and high-field carrier transport properties, which have been studied with ensemble Monte Carlo simulation techniques. A full-band Monte Carlo device simulator is being developed in close cooperation with the Computational Electronics group at Boston University. The in-house availability of reliable microscopic models has allowed recently the study of both HgCdTe avalanche photodetectors and GaN- and ZnO-based LEDs (including first-principles investigations of non-radiative recombination processes).

Publications in 2011

1)         S. Chiaria, M. Goano, E. Bellotti, “Numerical study of ZnO-based LEDs”, IEEE J. Quantum Electron., vol. 47, n. 5, pp. 661-671, 2011.

2)         F. Bertazzi, M. Goano, E. Bellotti, “Calculation of Auger lifetime in HgCdTe”, J. Electron. Mater., vol. 40, n. 8, pp. 1663-1667, 2011.

3)         M. Goano, S. Chiaria, M. Calciati, F. Bertazzi, G. Ghione, M. Meneghini, M. Ferretti, G. Meneghesso, E. Zanoni, E. Bellotti, D. Zhu, C. Humphreys, “Effects of dislocation density on injection and temperature sensitivity of InGaN LED emission spectra: a combined experimental and simulation approach”, 9th International Conference on Nitride Semiconductors (ICNS-9), Glasgow, U.K, July 2011.

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