Università degli Studi di Pavia

Dipartimento di Ingegneria Industriale e dell'Informazione}

Research activity

1.      Optical Chaotic Cryptography

V. Annovazzi Lodi, M. Benedetti 

Collaborations: European Network `Picasso', Università  di Padova, Università de L'Aquila

1.         Optical Techniques for micromachined devices

V. Annovazzi Lodi, M. Benedetti, G. Silva

Collaborations: STMicroelectronics, Dipartimento di Ingegneria dell'Informazione dell'Università di Pisa, IGM-CNR Pavia, IFAC-CNR Firenze, Dipartimento di Biochimica e Chimica Farmaceutica dell'Università di Pavia, Dipartimento di Biofisica dell'Università di Genova


3.      Microoptics for Photodetectors Arrays

G. Martini

Collaborations: Megaframe Consortium, CH, GB, I


 4.      3D imaging by optical telemetry

G. Martini

Collaborations: University of Trento, University of Modena e Reggio Emilia


5.      CMOS Transceivers and Building Blocks for RF Applications

R. Castello, D. Manstretta, A. Moroni, M. Sosio, N. Codega

Collaborations: Marvell, Broadcom


6.      Research activity on CMOS circuits and systems for mm-wave wireless data exchange, silicon photonics for optical communications and ultrasound for medical diagnostic

A. Ghilioni, A. Mazzanti, F. Montecchi, F. Svelto

Collaborations: Università di Modena, Politecnico di Milano, STMicroelectronics



F. Maloberti

Collaborations: Conexant Systems, EPFL, FBK-irst, INAOE, National Polytechnic Institute of Mexico, National Semiconductor, ST-Ericsson, STMicroelectronics, University of Extremadura, University of Ferrara, University of Milano-Bicocca


F. Maloberti

Collaborations: IIT Kharagpur, INAOE, National Polytechnic Institute of Mexico, National Semiconductor, University College Cork, University of Macau



F. Maloberti

Collaborations: CNR-IMM Lecce, EPFL, ESA, FBK-irst Trento, INFN, INAF, Polytechnic of Milan, Thales Alenia Space, University of Extremadura, University of Milano-Bicocca, University of Perugia, University of Rome II


10.   Monolithic pixel sensors for charged particle tracking applications

L. Ratti

Collaborations: Università  di Bergamo, Università di Bologna, Università dell'Insubria, Università di Pisa, Università di Trieste, Istituto Nazionale di Fisica Nucleare, Fermi National Accelerator Laboratory, Batavia, USA, Rutherford Appleton Laboratory, Didcot, UK, IPHC, Strasbourg, France


11.   Characterization of deep submicron CMOS technologies

L. Ratti

Collaborations: Università di Bergamo, Istituto Nazionale di Fisica Nucleare, CERN, Geneva, Switzerland

12.   Vertical integration CMOS technologies for monolithic pixel detectors

L. Ratti

Collaborations: Università di Bergamo, Università di Bologna, Università dell'Insubria, Università di Pisa, Università di Trieste, Istituto Nazionale di Fisica Nucleare, Fermi National Accelerator Laboratory, Batavia, USA


13.   Radiation tolerance in CMOS devices and circuits

L. Ratti

Collaborations: Università di Bergamo, Istituto Nazionale di Fisica Nucleare, Università di Pisa, CERN, Geneva, Switzerland


14.   Fast front-end electronics in nanoscale CMOS technologies for high resolution event timing

L. Ratti

Collaborations: Università di Bergamo, CERN, Geneva, Switzerland


15.   Noise in circuits and systems

G. Martini, V. Svelto

Collaborations: Stelar s.r.l, Mede (PV)


Optical Chaotic Cryptography

V. Annovazzi Lodi, M. Benedetti

Injection phenomena and chaos in semiconductor lasers is a research topic we started years ago, by considering the case of two coupled lasers, where the power exchange is known to lead to phase locking. At very low levels of coupling, we had found, and described, the so-called injection modulation effects. At higher levels of coupling, by using the Lang-Kobayashi rate equations to model the laser diode, we have been able to study the complete evolution from the first locking region to bifurcation, multi-periodicity and chaotic regime. However, not only is the chaotic behaviour interesting for a better understanding of the source dynamic properties, but it also leads to new potential applications. Among them, we are presently working on secure transmission, testing different schemes for cryptography of optical messages using chaos.

Basically, at the transmitter a master chaotic generator hides the message in chaos, so that it cannot be recovered by standard methods, such as filtering, either in time or frequency domain. At the receiver a slave system, synchronized to the master, is able to draw out the message from the otherwise unrecognizable waveform. This approach has been applied not only to lasers driven to chaos by mutual injection, but also to a laser driven to chaos by back-reflection from an external mirror.

In the last years, experimental results on transmission of analog and digital messages have been obtained, using DFB lasers in a fiberoptics setup. It has been demonstrated that chaos can efficiently mask a message in the GHz range, and that robust synchronization, and message extraction, can be achieved by using a matched laser couple, i.e., two lasers grown in close proximity on the same wafer. On the other hand, message extraction cannot be performed by a laser with different parameters, which demonstrates the security of the approach. Both amplitude and phase modulation cryptographic transmission have been studied experimentally.

Wavelength conversion for channel switching in multiwavelength (WDM) networks has been also demonstrated.

This research has been carried on in cooperation with a european network of universities and research centers, and has been funded by the European Community on the 5th and 6th Framework Programmes (Project PICASSO). This project has lead to the realization of integrated optics modules for secure transmission, based on chaos, of analog and digital signals in the GHz range, both in baseband and on a subcarrier. Investigations on chaotic cryptography have been also carried out in the national framework, in cooperation with the Universities of Padova and L'Aquila.

Other applications based on optical chaos have been also considered, such as the generation of periodic chaos for sensing.

Moreover, methods based on chaos analysis have been applied to study the EEG traces of patients suffering from epilepsy.


Optical Techniques for micromachined devices

V. Annovazzi Lodi, M. Benedetti, G. Silva

In 2011, we continued the activity related to the optical characterization of one dimensional, vertical photonic crystals (PhC), fabricated by the Universit\`a di Pisa by photo-electro-chemical-etching of silicon.

In particular, we were involved in the application of these Si photonic crystals for label-free biosensing. This activity was carried on in the framework of the Cariplo Foundation 2007 project ``Optical biosensor for the detection of amyloid fibrils-ligands interactions'' and the PRIN-MIUR 2007 project ``Photonic Crystal Optofluidic Microsystems for Biosensing''. In these projects, we worked on the optical characterization of PhC devices and on the evaluation of the optical response of sensing devices, based on the silicon micromachined photonic crystals, for refractive index measurements, in chemical and biochemical applications. In particular, the results of the optical characterization measurements gave important feedback on the optical quality and uniformity of the microstructures, required for improving the device layout and the fabrication process. In 2010, we started to work on a new project funded by Fondazione Alma Mater Ticinensis, Pavia, devoted to the use of vertical PhCs as three-dimensional micro-incubator for cell culturing and as transducer for cellular activities involving morphological changes.

We also carried on research activities in collaboration with Advanced System Technologies of STMicrolectronics in the field of lab-on-chip devices for real-time polymerase chain reaction (PCR) and for cells handling by means of dielectrophoresis.

Pubblications 2011

1)         G. Barillaro, A. Diligenti, L.M. Strambini, S. Surdo, S. Merlo, Alcohol-infiltrated one-dimensional photonic crystals, pp. 33-37 in “Sensors and Microsystems, Series: Lecture Notes in Electrical Engineering”, Vol. 91, G. Neri et al. Eds., Springer, 2011.

2)         S. Surdo, L.M. Strambini, G. Barillaro, F. Carpignano, S. Merlo, Silicon micromachined photonic crystal integrated in an opto-fluidic microsystem, International Workshop Biophotonics 2011, Parma, 8-10 Giugno 2011.

3)         S. Merlo, F. Carpignano, G. Silva, G. Barillaro, S. Surdo, G. Mazzini, S. Raimondi, M. Stoppini, Fluorescence detection of fibrillar proteins on silicon microstructures, International Workshop Biophotonics 2011, Parma, 8-10 Giugno 2011.

4)         S. Merlo, F. Carpignano, G. Silva, G. Barillaro, S. Surdo, G. Mazzini, S. Raimondi, M. Stoppini, Fluorescence detection of fibrillar proteins on silicon microstructures, International Workshop Biophotonics 2011, Parma, 8-10 Giugno 2011.

5)         S. Surdo, L.M. Strambini, G. Barillaro, S. Merlo, F. Carpignano, High-order one-dimensional silicon photonic crystals with a reflectivity notch at λ = 1.55 μm, 16th Italian Conference on Sensors and Microsystems - AISEM, Roma, 7-9 Febbraio, 2011.

6)         S. Merlo, G. Barillaro, F. Carpignano, S. Surdo, V. Leva, A. Montecucco, G. Mazzini, A cell-based optical biosensor exploiting silicon micromachined photonic crystals: a new tool for monitoring cellular activities, Convegno congiunto IGM-DGM, IGM-CNR, Pavia, 21-23 Febbraio 2011.

7)         S. Merlo, F. Carpignano, G. Barillaro, S. Surdo, L.M. Strambini, High-order one-dimensional silicon micromachined photonic crystal with a reflectivity notch at $\lambda $ = 1.55 $\mu $ m, B4-2 in Fotonica 2011, 13° Convegno Nazionale delle Tecnologie Fotoniche, Genova, 9-11 Maggio 2011, AEIT .

8)         S. Merlo, G. Silva, F. Carpignano, G. Barillaro, S. Surdo, L.M. Strambini, Vertical high-order 1D silicon photonic crystals for integrated opto-fluidic microsystems, P-08 in Fotonica 2011, 13° Convegno Nazionale delle Tecnologie Fotoniche, Genova, 9-11 Maggio 2011.

9)         F. Carpignano, S. Merlo, G. Silva, G. Barillaro, S. Surdo, L. M. Strambini, V. Leva, A.~Montecucco, V. Giansanti, I. Scovassi and G. Mazzini, Una nuova citometria “live” e “label-free” con microsistemi a cristalli fotonici in silicio, Lettere GIC, Vol. 20, Num. 3, pp. 13-18, 2011.


Microoptics for Photodetectors Arrays

G. Martini

As a follow-up of an FET European Project MEGAFRAME we continued research activity on the implementation and characterization of micro-optical elements for the recovery of the fill-factor in image photo detectors of large dimensionality.

An Optical Test Bench suitable to measure both Concentration and Back Focal Length of optical microlens arrays has been designed and implemented. The Optical Test Bench is easy to use and PC-controlled.

Using an array of 32x32 plano-convex microlenses, we demonstrated an increase of the detection sensitivity of a SPAD (Single Photon Avalanche Detector) array of 32x32 pixels, 50-$\mu$m pitch, up to a factor of 35 [1]. Repeatability of concentration factor and back focal length measurements have been reported.

Pubblications 2011

1)         Donati, S.; Martini, G.; Randone, E.; ``Improving Photodetector Performance by Means of Micro-Optics Concentrators'', Lightwave Technology, Journal of , IEEE, vol.29, no.5, pp.661-665, March 1, 2011, doi: 10.1109/JLT.2010.2103302


3D imaging by optical telemetry

G. Martini

Activities have been carried on the design and implementation of 3-D camera based on a new CMOS-compatible photo-detector providing an internal demodulation mechanism. The device has on-board pixel processing of the phase-to-distance signal and works in connection with a laser illuminator emitting 0.2 to 4 W of optical power modulated at a frequency of 20 to 50 MHz, to cover a range of distance 5 to 50 m with resolution of 1-5 cm. [1], [2].

Pubblications 2011

1)         Betta, G.D.; Donati, S.; Hossain, Q.D.; Martini, G.; Pancheri, L.; Saguatti, D.; Stoppa, D.; Verzellesi, G.; , ``Design and Characterization of Current-Assisted Photonic Demodulators in 0.18- $\mu$m CMOS Technology'', Electron Devices, IEEE Transactions on , vol.58, no.6, pp.1702-1709, June 2011, doi: 10.1109/TED.2011.2126578


CMOS Transceivers and Building Blocks for RF Applications

R. Castello, D. Manstretta, A. Moroni, M. Sosio, N. Codega

During the year 2011 the group has continued to carry on research in the area of analog circuit and systems in particularly those intended for radio frequency (RF)applications. These activities are partially supported by a Marie Curie FP7“ people - IAPP program started in 2009.  called "Adaptive transceiver for wireless communications" and partially supported by a direct Grant from Marvell Italy.

The aim of the Marie Curie project (which includes Marvell Italy, Marvell USA, ERICSSON central reserch in Sweden and Lund University also in Sweden) is to verify the concept of adaptive optimization in the design of a mobile transceiver in order to significantly improve its energy efficiency thereby extending its battery life.

In general the reserch activity of the group has continued to focus on the definition of the architecture and the realization in deeply scaled CMOS technologies of the key enabling blocks for several systems like digital video tuners, cell phone and millimeter wave transceivers. Within the very broad area of cell-phone transceivers, the group is continuing the on-going reserch activity on Multi-standard/Multi-mode transceiver with special focus on reconfigurable transmitters, highly digital receivers and very low power transceiver for personal area communications standards e.g. Zig-Bee. More specifically the reserch activity regards the following circuit blocks. All Digital PLL for multi-standard transmitter. RX Base band merged filters A/D converters. Linear RF power amplifier. High efficiency millimeter-wave CMOS oscillators. Broadband balun-LNA.

In the following the key ideas for some realized circuits are outlined.

All digital PLL building blocks

Nowadays, in the design of a mobile transmitter, the frequency synthesis seems to be more and more a digital stuff. Differently than for the rest of the radio, in the case of phase-locked-loops (PLL) the digital revolution has been enabled by the possibility to efficiently quantize time and frequency variables.

The resolution in time and frequency demanded for a full digital approach is not less challenging than its analog counterpart. For example, in the case of the GSM the required phase noise (PN) of -165dBc/Hz @ 20MHz demands also a DCO frequency resolution below 1 kHz when a carrier of 900MHz is used. At the same time, if an in-band phase noise below -105dBc/Hz is sought, a TDC time resolution close to 5ps is required for a 2GHz output carrier and a 26MHz reference clock. Both these targets can be reached with a fractional-N ADPLL that uses a dither-less DCO able to meet GSM specs and a 2- dimensional highly linear Vernier TDC. In addition to this, digitally assisted locking and calibrations allow a fast phase/frequency locking and the implementation of two-point modulation.

The modulation of the signal acting directly at the level of the frequency synthesizer is becoming common for standard using phase or frequency modulations (e.g. GSM) [1]. However, thanks to the advantages given by a digital approach in terms of calibration and re-configurability, the attempt is to displace the traditional direct-up architecture through the use of polar or out-phasing techniques even when non-constant envelope standard are used (e.g. WCDMA).

In this research activity we have realized and tested an ADPLL for GSM transmitter capable to implement wide-band direct phase modulation.

Filtering SD ADC

The analog base-band in a receiver chain is generally a cascade of filtering stages and variable-gain amplifiers/attenuators that minimize the dynamic range required at the input of the analog-to-digital converter (ADC). Although the presence of several building blocks allows an easier optimization of the receiver, this advantage is paid in terms of cost and power consumption. The path towards a software-defined radio (SDR) goes through the reduction of the base-band analog section of a wireless receiver in favor to a more flexible digital one. This challenging goal can be approached moving the ADC as close as possible to the antenna.

In a wireless environment, the replacement of the entire analog base-band with a single ADC is impaired by the capability of the converter to detect a small signal surrounded by strong interferers. One of the possibilities to overcome this fundamental limit is to embed into the ADC the filtering action necessary to prevent the saturation of the quantizer. However, this operation must be achieved without producing an increase of the in-band noise or in the power consumption with respect to the filter-ADC cascade alternative.

In this research activity, an ADC implementing the entire analog base- band of a DVB-T/ATSC tuner was realized. The proposed solution combines in the same feedback loop interferer filtering and signal digitization. The high dynamic range required to place the ADC directly at the mixer output is obtained exploiting three intrinsic properties of the structure. First, a grounded capacitance at the input of the ADC absorbs the largest part of the out-of-band interferers coming from the mixer without adding distortion components. Second, both analog and quantization noise are reduced by an in-band shaping that is not present when the filter is placed in front of the ADC. Third, the digital-to- analog converter (DAC) feedback path allows to synthesize a couple of complex conjugate poles leading to a steeper filtering profile than a simple two-real-poles cascade.

ZigBee Receiver

In the last decade, in order to reduce the cost of wireless interconnections, WLAN/ WPAN systems were proposed for data sharing amongst a small group of users. In this environment, the easier management of the clients has allowed to discard the star-mesh architecture in favor of a more flexible peer-to-peer configuration. Within this evolving scenario, the ZigBee and the other wireless sensor networks (WSN) standards represent an additional step towards the creation of an even more flexible system able to reshape itself dynamically. These systems do not require any base-station being formed by autonomous short-range wireless nodes.

In a ZigBee network, since the high density of units makes the system more flexible and relaxes the sensitivity of the single receiver, performance is exchanged with the possibility of having long-lasting and cheap devices. Unfortunately, high efficiency and low-cost tend to trade-off with each other making it difficult to achieve both of them simultaneously. As an example the use of resonant loads minimizes power consumption, while an inductor-free approach reduces the cost by saving die-area.

During this research, ZigBee receivers based on the LMV cell that can give both power and area saving through current and circuit reuse, were developed. In the standard LMV cell quadrature down-conversion is performed by cross-coupling two identical cells. To overcome this limitation an alternative receiver architecture that uses a single LO together with an LNA with I and Q outputs was introduced. Its main drawback is the extra noise associated with the circuits that performs the quadrature. However, in the case of sensor networks like ZigBee, the noise figure requirements are not particularly challenging, making it feasible to perform quadrature in the RF signal path.

Pubblications 2011

1)         Vercesi, L.; Fanori, L.; De Bernardinis, F.; Liscidini, A.; Castello, R.; , "A dither-less all digital PLL for cellular transmitters," Custom Integrated Circuits Conference (CICC), 2011 IEEE , pp.1-8, 19-21 Sept. 2011

2)         Sosio, M.; Liscidini, A.; Castello, R.; De Bernardinis, F.; , "A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC," ESSCIRC (ESSCIRC), 2011 Proceedings of the , pp.391-394, 12-16 Sept. 2011

Research activity on CMOS circuits and systems for mm-wave wireless data exchange, silicon photonics for optical communications and ultrasound for medical diagnostic

A. Ghilioni, A. Mazzanti, F. Montecchi, F. Svelto

The following research topics are being adressed: mm-wave transceivers for short range wireless wide-band communications, silicon photonics transceivers for ultra high data rates, devices for ultra-sound applications.

mm-Wave Circuits

An intense research activity toward the realization of mm-wave integrated circuits and systems has been carried out in the recent past, targeting several different applications: from Gb/s wireless data transfer in local area networks to automotive cruise control, from remote sensing to medical imaging.

Transceivers for high rate wireless video down-load are expected to be pervasive in consumer products shortly, taking advantage of low-cost, compact solutions offered by CMOS technologies.

In 2011 we have presented a complete receiver front-end suited for Gb/s communications meeting the specifications of ECMA standard.

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20$\%$, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector – charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low.

Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over 13 GHz bandwidth, 22.5 dBc integrated phase noise while consuming 84 mW.

During 2011 we have published the results of our work on mm-wave quadrature Voltage Controlled Oscillators (VCOs) and prescalers, the two most critical blocks of a PLL. New circuit solutions have been introduced.

The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56–60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.

Circuits for Silicon Photonics

As the speed of data transfer increases at all communication levels, from network down to chip level, copper-based connections are reaching their performance limits in terms of distance and error rates. In particular, the main obstacles are becoming dispersion, attenuation and crosstalk along the transmission channel. All of these limits can be overcome by the adoption of optical communications. However, traditional optical transceivers are expensive.

In the recent past a new process technology, called silicon photonics, has been identified as an attractive alternative to traditional optical transceivers, since it enables monolithic optoelectronic device integration together with electronic circuits in a low-cost CMOS process and thus paves the way to pervasive high speed communications at low cost and low power.

During 2010 we have started a new research aimed at the investigation of alternative circuit solutions for a full optical receiver targeting silicon photonics applications, ensuring operation at a data rate equal or higher than 25Gbps and a BER of better than 10$^{-12}$.

The first test-chip realized in the framework of this project is a full receiver for 25Gbps silicon photonics applications, realized in 65nm LPGP CMOS technolog. The test-chip, intended for electrical testing since no integrated photodiode is presently available, includes electrical I/O interconnections, a Trans-Impedance Amplifier (TIA), a Limiting Amplifier (LA) and an output buffer (BUF).

Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In our work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44µA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz∙Ω/mW.

Interface ICs for ultrasound imaging

The recent development of silicon microelectronic technologies following the "More than Moore" approach (which is alternative to the traditional device scaling, known as "More Moore") have made processes with many diversified active components available. These technologies can be used to design highly integrated and fully customized circuits for applications that are based on discrete components interfaces. An example is the co-integration, on the same silicon substrate, of high-speed mosfets, bipolar transistors and power mosfets (LDMOS. This technology can be used to address systems requiring simultaneously high-voltage and low noise interfaces such as ultra-sound sensors and imagers, widely adopted in industrial and medical applications. In our work, we have introduced a linear power amplifier (PA), based on a closed-loop resistive feedback topology built around a single gain stage, intended as driver of piezoelectric transducers for medical ultrasound imaging. Prototypes, realized in BCD6-SOI, show the following performances: 90Vpk-pk output signals on 100Ω//150pF load with more than 60$\%$ power efficiency, 720MHz GBW, better than -43dB HD2, with quiescent power dissipation of 37mW only. To the best of authors’ knowledge, this is the first integrated linear amplifier suited for ultrasound harmonic imaging systems.


Pubblications 2011

U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, F. Svelto:“ A mm-wave Quadrature VCO based on Magnetically coupled resonators”, IEEE International Solid State Circuits Conference (ISSCC), 21-23 Febbraio 2011, San Francisco, U.S.A., p. 280-281.

A. Ghilioni, U. Decanis, E. Monaco, A. Mazzanti, F. Svelto: “ A 6.5mW inductorless CMOS frequency divider by-4 operating up to 70GHz”, IEEE International Solid State Circuits Conference (ISSCC), 21-23 Febbraio 2011, San Francisco, U.S.A., p. 282-283.

A. Mazzanti, A. Sosio, M. Repossi, F. Svelto: “A 24GHz Subharmonic direct conversion receiver in 65nm CMOS”.IEEE Transaction on Circuits and Systems – I regular papers, Volume 58,  No. 1,  Gennaio 2011, p.88.

F. Vecchi, S. Bozzola, E. Temporiti, D. Guermandi, M. Pozzoni, M. Repossi, M. Cusmai, U. Decanis, A. Mazzanti, F. Svelto: “A Wide-band Receiver for Multi-Gbit/s communications in 65nm CMOS”. IEEE Journal of Solid State Circuits, Volume 46,  No. 3,  Marzo 2011, p.551.

U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, F. Svelto: “A low-noise quadrature VCO based on magnetically coupled resonators and a wide-band frequency divider at millimeter waves”. IEEE Journal of Solid State Circuits, Volume 46,  No. 12,  Dicembre 2011, p.2943.



F. Maloberti

This research activity aims at different design targets. Generally speaking, it is focused on design, modeling, and testing of analog and mixed analog-digital systems for signal processing purposes using CMOS technology, including both continuous-time and discrete-time (switched-capacitor) approaches, with particular emphasis on low-power and low-voltage issues.

In particular, we studied a single-inductor 4-outputs DC-DC buck converter. In order to independently regulate the four output voltages, a multiple control loop operates on linear combinations of the output voltage errors [1]. An original self-boosted snubber circuit enables load power switches control signals boosting without area and power efficiency penalties. The circuit, fabricated using a 0.5-$\mu$m CMOS process, provides four output voltages that can be independently regulated from 0 V to the used supply voltage $-500$~mV. The supply voltage can range from 2.3 up to 5~V. The overall minimum and maximum output currents are 0.15 and 1.8~A, respectively. The measured maximum cross regulation is 40~mV/V with a peak of power efficiency equal to 85\%.

Moreover, we developed a new low order time variant digital $\Sigma\Delta$ MASH modulator for fractional frequency synthesizers [2]. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the synthesizer.

We also introduced a Figure-of-Merit to compare the remotely powered communication systems [3]. The important parameters for remote powering and also communication are identified. The effect of ASK based communications on remote powering performance is analyzed by representing the challenges of power transfer during data transmission. This Figure-of-Merit is introduced to compare different modulation types in terms of powering and communication performances.

In addition, we studied a pseudorandom number generator that requires very low resources from the hardware design point of view [4]. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary low-complexity linear feedback shift register. We developed a predictability and periodicity analysis of the sequences generated by this architecture to show that the system is a good candidate to be used for applications requiring high-quality pseudorandom sequences in portable devices. The statistical behavior of this solution is also validated by tests from the National Institute of Standards and Technology. The generated pseudorandom sequences pass all tests at both the level-one and level-two approaches.

We developed a readout circuit for label-free DNA detection based on piezo-resistive MEMS cantilevers [5]. The circuit is designed to have high sensitivity and a precise calibration block in order to deal with possible large variation of the cantilever resistance due to technological mismatch effects. The readout channel has been electrically tested showing, as preliminary results, a total differential dynamic range of 35~dB with 15~$\mu$V as best input resolution, a static offset compensation of about 78~dB and a common-mode rejection of about 58~dB with about 2.2\% of linearity, which demonstrates the suitability of the proposed architecture for the target application. The chip consumes about 10~mW from a 3.3~V power supply, while the area occupation is of about 1.05~mm${^2}$ (pad excluded).

Class-D amplifiers exhibit high efficiency in spite of their simple implementation and, therefore, they are often used in portable devices with typical THD performance of the order of $-65$~dB. Presently, the possibility of using class-D amplifiers in applications requiring better THD ($\rm{THD} < -85$~dB) is being investigated, in consideration of their possible application in huge markets (like high-performance audio). For this reason, the THD performance of conventional class-D structures is not enough and new topologies have to be analyzed and implemented. Therefore, we investigated high-order class-D structures, to achieve the target THD performance. Among them, we selected a 3$^{\rm{rd}}$-order fully-differential class-D amplifier, which has been implemented in a 0.18-$\mu$m CMOS technology, starting from a previously available 1$^{\rm{st}}$-order class-D structure [6]. The measurements on the realized 3$^{\rm{rd}}$-order device show a $\rm{THD} \approx -91$~dB with $-1$~dB$_{\rm{FS}}$ input signal, about 30~dB better than the 1$^{\rm{st}}$-order structure.

Moreover, we designed a 1-A DC-DC converter with embedded digital controller in 65-nm CMOS technology. The digital controller, based on a customized, multi-function SAR ADC, occupies 0.038~mm$^{2}$ and consumes 115.5~$\mu$A from a 1.2-V supply, making the DC-DC converter suitable for portable applications [7]. The DC-DC converter implements Continuous-Conduction Mode (CCM) control for high-current loads, a Pulse- Skipping (PSK) feature, in order to keep high efficiency at light loads, and automated switching between these two modes, in order to guarantee the best possible transient performance and efficiency.

Bulk-driven MOS transistors lead to a compact low-voltage/low-èpower input stage implentation. In tihis respect, the response of a bulk-driven MOS input stage over the input common-mode voltage range was discussed and experimentally evaluated [8]. In particular, the behavior of the effective input transconductance and the input current was studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35-$\mu$m CMOS technology, demonstrated that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source-bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk-driven differential pair was proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5-V second-order operational transconductance amplifier (OTA)-C lowpass filter. Experimental results validated the effectiveness of the approach.

We also designed a fully differential operational transconductance amplifier (OTA) suited to low-voltage operation [9]. The input differential stage is based on a bulk-driven pair whose effective transconductance is enhanced by means of a partial positive feedback loop. The DC output common-mode voltage is controlled by means of a low-voltage feedback network, which is also based on bulk-driven devices. The OTA was included in a 1.2-V tunable fully differential second-order OTA-C lowpass filter. Experimental results, obtained in standard 0.35-$\mu$m CMOS technology, showed a dynamic range around 70~dB with a total power consumption of 382~$\mu$W for a filter cutoff frequency of 3~MHz. [12]

Two different circuit techniques to enhance the effective transconductance of a CMOS bulk-driven differential input stage were also studied [10]. Both approaches rely on a partial positive feedback, which leads to improved values for the DC gain and the gain-bandwidth product. The operation principle of the first solution is based on modifying the effective conductance of the active load of the input stage, while the second method acts directly on the input differential pair. The suitability of these techniques was demonstrated by the design of operational transconductance amplifiers operating at two different supply voltages, i.~e., 2.4 and 1.0~V. Besides, the overall design of two applications, namely a 3~V input/output rail-to-rail operational amplifier with high linearity and a 1.2~V second-order OTA-C low-pass filter, was addressed. Simulated results obtained in standard 0.35 $\mu$m CMOS technology demonstrated the applicability of the solutions introduced.

Finally, a fully differential (FD) voltage buffer suited to low-voltage operation and able to operate over a wide voltage range was presented [11]. The buffer core is based on a FD difference amplifier including bulk-driven MOS transistors as input devices. The common-mode (CM) component of the buffer output voltage is controlled by means of a bulk-driven CM feedback network that features an extended operating voltage range. The buffer was designed and fabricated in 0.35-$\mu$m CMOS technology for operation with a 1.5-V supply. Experimental results confirm the performance of this solution.

Pubblications 2011

1)         M. Belloni, E. Bonizzoni, P. Malcovati, and F. Maloberti, ``A high efficiency 4-output single inductor DC-DC buck converter with self boosted snubber'', Analog Integrated Circuits and Signal Processing, Vol. 67, No. 2, pp. 169-177, May 2011.

2)         V. R. Gonzalez-Diaz, A. Pe\~{n}a Perez, and F. Maloberti, ``Use of time variant digital $\Sigma\Delta$ for fractional frequency synthesizers'', Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 169-172, May 2011.

3)         E. G. Kilinc, O. Atasoy, C. Dehollain, and F. Maloberti, ``FoM to Compare the Effect of ASK Based Communications on Remotely Powered Systems'', Proceedings of IEEE Conference on Ph.~D. Research in Microelectronics and Electronics (PRIME), pp. 29-32, July 2011.

4)         V. R. Gonzalez-Diaz, F. Pareschi, G. Setti, and F. Maloberti, ``A pseudorandom number generator based on time-variant recursion of accumulators'', IEEE Transactions on Circuits and Systems II -- Express Briefs, Vol. 58, No. 9, pp. 580-584, September 2011.

5)         F. Borghetti, N. Massari, D. Stoppa, A. Adami, L. Lorenzelli, and F. Maloberti, ``An analog readout circuit with offset calibration for cantiliver-based DNA detection'', Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 323-326, September 2011.


F. Maloberti

Our research group studied various architectures for analog-to-digital (A/D) and digital-to-analog (D/A) conversion. The activity is focused on implementation, modeling and characterization of data converters for either low-frequency and high-resolution applications or high-speed applications, with special emphasis on low-voltage and low-power design. In particular, we spent a lot of efforts on the design and optimization of sigma-delta ($\Sigma\Delta$) modulators either low-pass and band-pass.

In the frame of this research activity, we developed an ADC that uses the successive-approximation method to obtain 8~b up to 400~MS/s with very low power using a 1.2~V supply [1]. Key features of the architecture are a resistive DAC and a 2-b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024~mm${^2}$.

Moreover, we studied a third-order $\Sigma\Delta$ modulator, suitable for high-resolution low-power sensor systems, consumes 140~$\mu$W to obtain 84-dB SNDR with $\rm{OSR} = 16$ and 100-kHz signal bandwidth [2]. The achieved FoM is 54~fJ/conversion-step. The DACs use a single resistive divider to generate 32 differential 5-b reference voltages. The proposed scheme totally cancels the error caused by gradient in the resistance values.

We also developed a low-power $\Sigma\Delta$ modulator which targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band [3]. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18~mW, thus yielding a FoM of 0.58~pJ/conversion-step. The area of the circuit, fabricated with a 0.18-$\mu$m analog CMOS technology, is 0.32~mm${^2}$. Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

In addition we studied a design methodology for dithered bus-splitting Multi stAge noise SHaping (MASH) digital $\Sigma\Delta$ modulators (DDSMs) [4]. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations confirm the theoretical predictions.

We developed an architecture for low-power $\Sigma\Delta$ modulators suitable for high-resolution portable sensor systems [5]. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-$\mu$m CMOS technology, obtains a peak SNDR of 88~dB over an input signal bandwidth of 100~kHz. The simulated power consumption is 125~$\mu$W with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31~fJ/conversion-step.

We studied methods for avoiding the slew-rate limit and the optimal design of hybrid Continuous-Time (CT) $\Sigma\Delta$ modulators with switched-capacitor (SC) DAC [6]. Limitations on performance due to finite bandwidth and slew-rate of the operational amplifier are analyzed. The use of multi-rate scheme made by a set of time-interleaved SC-DAC moderates the non-linear error caused by the limited slew-rate in mono-rate converter at equal slew-rate. Behavioral level simulations confirm the validity of this technique.

We developed a method that virtually doubles the oversampling ratio of a second order $\Sigma\Delta$ modulator [7]. Accounting for a limited cost, the resolution increases by about 2-bit and power just increases by few percents. Therefore, the FoM diminishes by a factor close to 3.5. Simulation at the behavioral level of this method verifies the operation. Circuit level schemes indicate that the architecture does not requires higher op-amp bandwidth. The method can be used with multi-bit quantizer without requiring additional efforts for the DEM.

We studied a new design methodology for reconfigurable quadrature band-pass $\Sigma\Delta$ modulator [8]. The methodology uses architectures, which locks various range of IF frequencies to the sampling frequency for lower order quadrature modulators. A generalized integrator based architecture is developed from the delay architectures. The method is presented with derivation of the base circuitry and with this base circuitry stringent performance can be satisfied by extending the work to cascading lower order quadrature modulators with possible image reduction techniques.

We made some observations on the resolution and tones of First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converters (LO TDCs) [9]. We analyze the architecture and governing equations of the LO TDC. We introduce equations to predict the resolution of the system ``LO TDC plus moving average filter'' and the frequency and amplitude of the largest amplitude tone in the spectrum of the TDC output when the input is constant. We developed a Matlab model of the LO TDC and implemented it on an FPGA. Finally, we compare analytical predictions of the amplitude and frequency of the largest tone in the spectrum with simulations and experimental results. The prediction of the powers and positions of the tones in the TDC output spectrum is fundamental for the design of the system in which the TDC has to be used.

The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12- 14 bits) has been studied [10], developing design methods that give rise to various Nyquist rate schemes resembling incremental converters. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are introduced.

We studied a design methodology for bus-splitting digital $\Sigma\Delta$ modulators (DDSMs) [11]. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations and experimental results confirm the theoretical predictions.

Moreover, we developed a new concept for an effective quadrature band-pass $\Sigma\Delta$ modulator and analyzed the high level implementation for a third order two-path scheme based on delay line [12]. The methodology uses an architecture which locks IF frequencies to the sampling frequency. Robustness of the structure against the mismatch is analyzed. Simulations at the behavioral level verify the architecture implementation which uses a novel switched capacitor scheme.

We studied a Time-Interleaved (TI) pipelined-SAR ADC with on-chip offset cancellation technique [13]. The design reuses the SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time. A 6 bit capacitive DAC is built as a flip-around MDAC for low inter-stage gain implementation.

The capacitive attenuation solutions in both 1$^{\rm{st}}$ and 2$^{\rm{nd}}$ DACs minimize the power dissipation and optimize conversion speed. Measurements of a 65-nm CMOS prototype operating at 160~MS/s and 1.1-V supply show 2.72-mW total power consumption. The SNDR is 55.4~dB and the FoM as low as 35~fJ/conversion-step.

Finally, we also developed a design technique for a double-delay based quadrature $\Sigma\Delta$ modulator [14]. The architecture uses a two-path scheme, which avoids mirror tones in the signal band and locks the intermediate frequency with the clock, thus avoiding the trimming requirement. The two-path architecture and time interleaving lead to an overall power reduction by a factor of 8.

Pubblications 2011

1)         H. Wei, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. Martins, and F. Maloberti, ``A 0.024-mm${^2}$ 8-b 400-MS/s SAR ADC with 2-b/cycle and resistive DAC in 65-nm CMOS'', IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 187-188, February 2011.

2)         A: Pe\~{n}a Perez, E. Bonizzoni, and F. Maloberti, ``A 84-dB SNDR 100-kHz bandwidth low-power single op-amp third-order $\Sigma\Delta$ modulator consuming 140~$\mu$W'', IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 477-478, February 2011.

3)         E. Bonizzoni, A. Pe\~{n}a Perez, F. Maloberti, and M. A. Garcia-Andrade, ``Two op-amps third-order $\Sigma\Delta$ modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption'', Analog Integrated Circuits and Signal Processing, Vol. 66, No. 3, pp. 381-388, March 2011.

4)         B. Fitzgibbon, M. P. Kennedy, and F. Maloberti, ``A novel implementation of dithered digital $\Sigma\Delta$ modulators via bus-splitting'', Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1363-1366, May 2011.

5)         A. Pe\~{n}a Perez, E. Bonizzoni, and F. Maloberti, ``A low-power third-order $\Sigma\Delta$ modulator using a single operational amplifier'', Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1371-1374, May 2011.

6)         O. Belotti, E. Bonizzoni, and F. Maloberti, ``Mono-rate and multi-rate hybrid continuous-time $\Sigma\Delta$ modulators with SC feedback DAC'', Proceedings of IEEE International Symposium on Signals, Circuits and Systems (ISSCS), June 2011.

7)         O. Belotti, A. Pe\~{n}a Perez, and F. Maloberti, ``Oversampling enhancement in $\Sigma\Delta$ modulators'', Proceedings of IEEE Conference on Ph.~D. Research in Microelectronics and Electronics (PRIME), pp. 241-244, July 2011.

8)         Y. B. Nithin Kumar, A. Patra, and F. Maloberti, ``Reconfigurable multi-band quadrature $\Sigma\Delta$ modulators'', Proceedings of Ph.~D. Research in Microelectronics and Electronics (PRIME), pp.~237-240, July 2011.

9)         F. Brandonisio, M. P. Kennedy, and F. Maloberti, ``Observations on the resolution and tones in first order noise shaping time-to-digital converters'', Proceedings of IEEE Conference on Ph.~D. Research in Microelectronics and Electronics (PRIME), pp. 17-20, July 2011.

10)     Y. Liu, E. Bonizzoni, and F. Maloberti, ``Digital assisted high-order multi-bit analog to digital ramp converters'', Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD), pp. 593-596, August 2011.

11)     B. Fitzgibbon, M. P. Kennedy, and F. Maloberti, ``Hardware reduction in digital $\Sigma\Delta$ modulators via bus-splitting and error masking -- Part I: constant input'', IEEE Transactions on Circuits and Systems I -- Regular Papers, Vol. 58, No. 9, pp. 2137-2148, September. 2011.

12)     Y. B. Nithin Kumar, E. Bonizzoni, A. Patra, and F. Maloberti, ``Two-path delay line based quadrature band-pass $\Sigma\Delta$ modulator'', Proceedings of IEEJ International Analog VLSI Workshop (AVLSIWS), pp. 65-69, November 2011.

13)     Y. Zu, C.-H. Chan, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, ``A 35-fJ 10-b 160-MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation'', Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 61-64, November 2011.

14)     Y. B. Nithin Kumar, E. Bonizzoni, A. Patra, and F. Maloberti, ``Two-path double delay line based band-pass quadrature $\Sigma\Delta$ modulator'', Electronics Letters, Vol. 47, pp. 1316-1317, November 2011.


F. Maloberti
This research activity is focused on design and implementation of interface circuits for integrated sensors. In a number of these electronic systems, the sensor and the circuitry are realized on the same chip, using standard integrated circuit (IC) technologies. In this case, the sensor is typically obtained with additional fabrication steps before or after the completion of the CMOS or bipolar process (pre- or post-processing steps). Obviously, these processing steps should not degrade the performance of the conventional IC devices on the chip. An additional topic addressed in this field is represented by interface/processing circuits for healthcare applications.

In the frame of this research activity, we designed a 32-channel integrated circuit (ASIC) designed for a multi-anode silicon drift detector for X-ray imaging and spectroscopy ($0.5 \div 100$~keV). The ASIC includes 32 read-out front-end channels (ROC), each consisting of a low-noise preamplifier, a second-order RC-CR pulse shaper, a peak stretcher, an amplitude and a peak discriminator, as well as a reset and pile-up rejection circuit. The ASIC includes also a digital configuration register, supporting daisy-chain connection, for setting the ROC parameters for signal processing. At room temperature the equivalent noise charge is 18~e$^{-}_{\rm{rms}}$ and the linearity error is lower than $\pm5$\% over the complete input range. The ASIC has been designed in a 0.35-$\mu$m CMOS technology with a 3.3-V power supply. A single ROC occupies an area of $200 \times 380$~$\mu$m$^{2}$. The area of the whole ASIC is $6500 \times 2260$~$\mu$m$^{2}$ and the power consumption is 0.4~mW per channel. This ASIC will be used in several applications related to space missions [1, 2, 3, 4, 5].

Moreover, we developed a low-cost integrated wide-range gas sensor interface based on a resistance-to-time converter [6]. The circuit in transistor level simulation achieves a linearity better than 0.5\% over a range of 6 decades, i.~e. 1~k$\Omega$~$\div$~1~G$\Omega$, without requiring any calibration or auto-ranging. The maximum sensing time is 0.5~s, while measuring the highest resistance value. The state-of-the-art of this measurement has been improved by extending the acceptable input resistance range, while lowering the maximum power consumption. Moreover, a very high linearity has been achieved by canceling the parasitic effects of the multiplexer addressing the sensor matrix.

We also designed an integrated smart label for tracing food information and monitoring its preservation conditions. The system includes humidity, temperature, and light intensity sensors with the respective interface circuits, an A/D converter, and a 13.56-MHz RFID transponder for transmitting and receiving data, as well as for gathering from an external reader the energy for recharging the on-board micro-battery and powering the transmitter [7, 8].

We also developed an integrated interface circuit for condenser MEMS microphones [9]. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order $\Sigma\Delta$ modulator and a fully-digital, single-bit, fourth-order $\Sigma\Delta$ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3~V, exhibits a current consumption of 215~$\mu$A for the analog part and 95~$\mu$A for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71~dB, with an input signal amplitude as large as $-1.8$~dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog $\Sigma\Delta$ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-$\mu$m CMOS process, occupies an area of 3~mm$^{2}$, including pads.

Moreover, the optimal matching between tag antenna and integrated circuit is crucial for maximizing delivered power in remotely-powered sensor systems [10]. We studied a method that maximizes conjugate matching between antenna with inductive reactive impedance and an integrated circuit with capacitive reactive impedance. Obtaining the desired conjugate impedance by the intrinsic antenna impedance excludes the need of an impedance matching network. This enables fully integrated sensor systems with further miniaturization. In this study the design of a meandered slot antenna with genetic algorithm optimization for an operation frequency of 2.45~GHz is developed. Investigations on constraints limiting the power link efficiency between reader and tag antenna at system level outline possible design actions and give rise to the design flow of the antenna. Simulation results on this architecture verify the performance of the miniaturized antenna.

In the field of interface/processing circuits for healthcare applications, we presented design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers [11, 13]. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product was discussed. To this end, a comparison of several types of low-voltage gain cell topologies was provided. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-$\mu$m CMOS technology to operate over a DC-to-20-MHz bandwidth. The proposed limiting amplifier draws 280~$\mu$A from a 2-V supply and achieves a voltage gain of 75~dB.

Finally, we developed a power-efficient CMOS limiting amplifier to be used as a basic building block for bioelectrical impedance phase angle measuring devices [12]. The limiting amplifier is intended for use in a wearable device for malnutrition status assessment. A high-sensitivity limiting amplifier tolerant of process spreads and mismatches was fabricated in 0.35-$\mu$m CMOS technology. The circuit was designed to operate over a DC-to-20-MHz bandwidth. Experimental results showed an input sensitivity of $-65$~dB and a power consumption of 560~$\mu$W from a 2-V supply.

1)         O. Kazanc, C. Dehollain, and F. Maloberti, ``Impedance-matched sensor-tag antenna design using genetic algorithm optimization'', Proceedings of International Symposium on Medical Information and Communication Technology (ISMICT), pp. 61-64, March 2011.

Monolithic pixel sensors for charged particle tracking applications

L. Ratti

Monolithic active pixel sensors (MAPS) in CMOS technology are considered very promising as a replacement or a valid competitor with CCD detectors in many applications. The main reason for the ever growing interest in CMOS MAPS lies in the possibility of integrating analog and digital processing electronics together with the sensor array in the same substrate, taking advantage of the large scale of integration and low power dissipation available through commercial CMOS processes. In the last few years, many efforts were made to extend the application field of CMOS MAPS to particle detection in high energy physics experiments. The interest of the particle physics community for MAPS sensors stems from them being a possible solution to the material budget issue put forward by the experiments to be run at the future high luminosity colliders. This research activity is concerned with a new implementation of CMOS monolithic active pixel sensors for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is read out by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, or deep n-well (DNW), available as a shielding layer for n-channel devices in deep submicron, triple well CMOS technologies. Several test structures have been designed and fabricated in 130 nm, 90 nm and 65 nm CMOS technologies to explore the limits of the proposed approach and evaluate charge collection efficiency, charge sharing among adjacent pixels and noise properties of the

readout electronics. In the same structures, also the issue of cross talk between the pixel level digital section and the detector has been addressed. DNW MAPS were proposed chiefly to comply with the intense data rates foreseen for tracking applications at the future high energy physics (HEP) facilities. Based on the proposed device, the first ever MAPS detectors with pixel-level data sparsification have been designed and produced. Tests of a 32x128 matrix on the beam line of the Proton Syncrotron at CERN, Geneva, proved that DNW MAPS represent a very promising solution for vertexing applications at the future high luminosity colliders.

Pubblications 2011

1)         L. Ratti et al., ÓThe SuperB silicon vertex trackerÃ’, \emph{Nucl. Instrum. Methods}, vol. A636, Supplement, pp. S168-S172, 2011.

2)         L. Ratti et al., ÓThin pixel development for the SuperB silicon vertex trackerÃ’, \emph{Nucl. Instrum. Methods}, vol. A650, pp. 169-173, 2011.

3)         L. Ratti et al., ÓBeam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processingÃ’, \emph{Nucl. Instrum. Methods}, vol. A617, pp. 234-237, 2011.

Characterization of deep submicron CMOS technologies

L. Ratti 

Deep submicron CMOS technologies are today widely used in mixed-signal front-end systems. They provide the required integration density and are very promising in terms of radiation hardness. This latter feature comes as a byproduct of the thickness reduction of both gate and

isolation dielectric layers, making CMOS devices less susceptible to ionization damage. As far as analog performances are concerned, the trend toward device scaling brings along the need of understanding the noise properties of transistors with channel lengths of a few tenth of a micron and below. In the framework of this research program, static and, particularly, noise characterization of deep submicron CMOS technologies has been performed, paying particular attention to short-channel effects and to parasitic noise contributions from gate and substrate resistance. The characterization has been extended to CMOS processes with minimum channel length of 350, 250, 180, 130, 90 and 65 nm. In the case of the 130, 90 and 65 nm technologies, where the gate oxide thickness is below 3~nm, a thorough analysis of the properties of the no longer negligible, direct, tunneling assisted gate current has been performed. Noise measurements, both in the drain and in the gate current, are carried out by means of purposely developed wide band transimpedance amplifiers. Furthermore, the study of the experimental noise data relevant to P and N-channel MOSFETs operated in weak and moderate inversion has been used to extract design criteria for low-noise, low-power analog blocks. Special attention is paid to the behavior of white and 1/f noise components as a function of the device geometry and operating region.

Pubblications 2011

1)         M. Manghisoni, L. Gaioni, L. Ratti, V. Re, G. Traversi, Ã’Noise and radiation hardness of 65~nm CMOS transistors and pixel front-endsÓ, \emph{Topical Workshop on Electronics for Particle Physics 2011}, Vienna, Austria, 26-30 September 2011.

Vertical integration CMOS technologies for monolithic pixel detectors

L. Ratti

Deep N-well CMOS monolithic active pixel sensors (DNW-MAPS) were proposed a few years ago to satisfy the requirements of the experiments at the future high luminosity machines, like the SuperB Factory and the International Linear Collider. They have the potential for incorporating both the low-material budget features of standard 3-transistor MAPS and the pixel-level sparsification capabilities of hybrid detectors. Recently, vertical integration, or 3D, processes have been taken into consideration for the design of 3D DNW MAPS. Three dimensional circuit manufacturing involves the independent fabrication of two or more planar circuits on different wafers, which are subsequently bonded together after precise alignment and thinning. Vertical integration technologies have already become quite popular among IC designers, as they can alleviate some important performance limitations correlated with CMOS feature size scaling. They are already widely used in the design of high density storage devices and promise to provide a means to overcome the bandwidth bottleneck in modern microprocessors by vertically integrating processor and memory subsystems in a single chip. Among the available three dimensional integration processes and techniques, the one provided by Tezzaron Semiconductor was chosen for the fabrication of the first 3D DNW-MAPS. Tezzaron 3D technology relies upon the vertical integration of two (or more) 130 nm CMOS wafers produced by Chartered Semiconductor (now part of Globalfoundries), which adopts a via first strategy for through silicon via (TSV) formation. In a three dimensional DNW MAPS, the analog layer includes the DNW sensor, the charge preamplier and the NMOS differential pair of a threshold discriminator. The PMOS mirrored load of the discriminator, which, for matching purposes, need to feature quite a large area, is integrated in the digital tier together with all of the logic blocks, to reduce parasitic collection by N-wells and improve the charge collection efficiency of the sensor. The set of logic functions performed by the top tier electronics includes token management for sparsified readout, control of global buses for data output and double hit and time stamp storage. Vertically integrated deep N-well monolithc sensors are also being considered for the detection of low energy beta particles. These applications are of particular interest in the field of biomedical imaging, for example in digital autoradiography of tritium radiolabeled biological specimens.

Pubblications 2011

1)         A. Manazza, L. Gaioni, L. Ratti, V. Re, G. Traversi, S. Zucca, Ã’Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0Ó, \emph{Il Nuovo Cimento della Societ\`a Italiana di Fisica}, vol. 34C, no. 6, pp. 57-59, Nov.-Dec. 2011.

2)         L. Ratti, Ã’Vertical integration technologies for vertex detectorsÓ, \emph{Il Nuovo Cimento della Societ\`a Italiana di Fisica}, vol. 34C, no. 6, pp. 106-110, Nov.-Dec. 2011.

3)         L. Ratti et al., ÓBeam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processingÃ’, \emph{Nucl. Instrum. Methods}, vol. A617, pp. 234-237, 2011.

4)         G. Traversi, L. Gaioni, M. Manghisoni, L. Ratti, V. Re,Ã’2D and 3D CMOS MAPS with high performance pixel-level signal processingÓ, \emph{Nucl. Instrum. Methods}, vol. A628, pp. 212-215, 2011.

5)         L. Ratti, L. Gaioni, M. Manghisoni, V. Re, G. Traversi, Ã’Vertically integrated monoli- thic pixel sensors for charged particle tracking and biomedical imagingÓ, \emph{Nucl. Instrum. Methods}, vol. A652, pp. 630-633, 2011.

6)         L. Ratti, L. Gaioni, A. Manazza, M. Manghisoni, V. Re, G. Traversi, Ã’First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applicationsÓ, \emph{8$^{th}$ international Hiroshima Symposium on the Development and Application of Semiconductor Tracking Detectors (HSTD-8)}, Taipei, Taiwan, 5-8 December 2011.

7)         A. Manazza, L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, S. Zucca, Ã’Vertical Integration Approach to the Readout of Pixel Detectors for Vertexing ApplicationsÓ, \emph{2011 IEEE Nuclear Science Symposium Conference Record}, pp. 641-647, 23-29 October 2011.

8)         L. Ratti et al., Ã’2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex TrackerÓ,  \emph{2011 IEEE Nuclear Science Symposium Conference Record}, pp. 1324- 1328, 23-29 October 2011.

9)         A. Manazza, S. Zucca, L. Gaioni, L. Ratti, G. Traversi, Ã’Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technologyÓ, \emph{7$^{th}$ Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)}, 3-7 July 2011, pp. 77-80, doi: 10.1109/PRIME.2011.5966221.

Radiation tolerance in CMOS devices and circuits

L. Ratti

Deep submicron CMOS technologies feature a considerable degree of radiation hardness, going along with lithographic scaling. This property can be profitably exploited in the design of radiation hard front-end electronics for high energy physics detectors and spatial applications. In order to assess their intrinsic radiation hardness features, CMOS transistors belonging to technologies from the 350~nm to the 65~nm node have been irradiated with $\gamma$-rays from a $^{60}$Co source and with 10~keV X-rays; subsequent changes in static, signal and noise parameters have been monitored. The results demonstrate that gate oxide thinning brings about improved radiation hardness as far as ionization damage is concerned, with some minor changes in low frequency noise of NMOS devices, likely to be related to charge trapping in shallow trench isolation oxides. However, the latter effects can be avoided by using purposely designed devices,

such as enclosed layout transistors, which prevent the formation of parasitic lateral transistors in parallel with the main device channel. Radiation effects studies, including neutron induced bulk damage, have been extended to CMOS monolithic active pixel sensors in a 130~nm CMOS process with triple well feature. The experimental results provides useful hints for more robust design of the next deep n-well MAPS generations.

Pubblications 2011

1)         L. Ratti, L. Gaioni, M. Manghisoni, V. Re, G. Traversi, Ã’TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs Ó, \emph{IEEE Trans. Nucl. Sci.}, vol.~58, no. 3, pp. 776-784, Jun. 2011.

2)         S. Zucca, L. Ratti, G. Traversi, S. Bettarini, F. Morsani, G. Rizzo, L. Bosisio, I. Rashe- vskaya, V. Cindro, Ã’Characterization of bulk damage in CMOS MAPS with deep N-well collecting electrodeÓ, \emph{12$^{th}$ European Conference on Radiation and Its Effects on Components and Systems (RADECS 2011)}, Sevilla, Spain, 19-23 September 2011.


Fast front-end electronics in nanoscale CMOS technologies for high resolution event timing

L. Ratti

Silicon vertex detectors at the next generation facilities, such as the Super-B Factory or the International Linear Collider, will need to fulfill very stringent requirements on

position and time resolution, material budget, readout speed and radiation tolerance. Deep-submicron CMOS tech?nologies, thanks to their large scale of integration, are widely used for the development of low noise front-end electronics for hybrid pixels and monolithic active pixel sensors (MAPS). Following the trend of commercial silicon foundries, there is a growing interest for CMOS processes with a minimum feature size below 100 nm. Such processes may help face the demand for higher in-pixel functionalities and will enhance local intelligence in the elementary cell with respect to peripheral readout electronics. A 65 nm CMOS techonology is expected to give some significant advantages in the design of dense readout systems for pixel detectors with respect to the 130 nm and 90 nm technologies (currently the focus of IC designers in the development of ASICs in future detector applications), such as better power/channel thermal noise trade-off and larger functional density. A readout chip, called Apsel65, among the first prototypes integrated in a 65 nm technology for tracking applications, was designed to help estimate the impact of nanoscale processes on the main parameters of front-end electronics for pixel detectors. Apsel65 takes advantage the triple well option of a 65 nm CMOS process manufactured by IBM for the design of so called deep N-well (DNW) MAPS featuring a 40 $\mu$m pitch. It also includes fast front-end channels chiefly conceived for the readout of high-resistivity, fully depleted detectors and suitable for high resolution event timing.

Pubblications 2011

1)         L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, Ã’Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensorsÓ, \emph{Nucl. Instrum. Methods}, vol. A650, pp. 163-168, 2011.

2)         L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, Ã’The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS nodeÓ, \emph{2011 IEEE Nuclear Science Symposium Conference Record}, pp. 1966-1971, 23-29 October 2011.

3)         M. Manghisoni, L. Gaioni, L. Ratti, V. Re, G. Traversi, Ã’Analog Design Criteria for High-granularity Detector Readout in the 65 nm CMOS TechnologyÓ,  \emph{2011 IEEE Nuclear Science Symposium Conference Record}, pp. 1961-1965, 23-29 October 2011.

4)         M. Manghisoni, L. Gaioni, L. Ratti, V. Re, G. Traversi, Ã’Design and tests of pixel readout circuits in 65~nm CMOSÓ, \emph{8$^{th}$ International Meeting on Front-End Electronics}, Bergamo, Italy, May 24-27 2011.

Noise in circuits and systems

G. Martini, V. Svelto

Signal envelope recovery in NMR signal acquisition at low SNR in unstable magnetic field

Continues the activity on noise error compensation of NMR signal acquired in unstable magnetic field. Previously developed method aimed at noise error compensation has been tested using ``real world" signals, demonstrating its applicability. Extensive measurements have been made on real NMR signal acquisition system. Accurate estimation of T1 and T2 from low SNR data have been obtained even in unstable magnetic field conditions [1].

Pubblications 2011

1)         Giuseppe Martini, Gianni Ferrante,``Noise bias correction in accumulated modulus NMR signal recover'', Noise and Fluctuations (ICNF), 2011 21$^{st}$ International Conference on, Proceedings, June 12-16, 2011, Toronto, Canada, pp.425-428, doi: 10.1109/ICNF.2011.5994361

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